The present invention relates to a semiconductor memory device, and more particularly to a delay circuit having a delay time corresponding to an environmental change, and a circuit of generating a bit line sense amplifier enable signal using the same.
In general, a semiconductor memory device such as a double data rate synchronous DRAM (DDR SDRAM) includes a plurality of memory cells that are enabled/disabled according to a plurality of addresses, and writes data to a corresponding memory cell or reads the data from the memory cell using these addresses.
Herebelow, a read operation for outputting stored data will be described.
When a word line selected by a row address is enabled, a plurality of memory cells connected to the word line operate so that a charge sharing occurs between the memory cells and bit lines connected thereto. At this time, there is a slight voltage difference between a bit line where the charge sharing occurs and a bit line bar where the charge sharing does not occur, and such a voltage difference is then sensed and amplified by a bit line sense amplifier.
FIG. 1 is a circuit diagram illustrating a partial configuration of a conventional semiconductor memory device.
Referring to FIG. 1, the conventional semiconductor memory-device includes a memory cell 110 configured to store data, an upper bit line separator 120A, a lower bit line separator 120B, a bit line equalizer 130, a bit line sense amplifier 140, a power supply 150 and a column selector 160.
Recently, a semiconductor memory device has adopted a sharing method where an upper memory cell, i.e., the memory cell 110, and a lower memory cell (not shown) share one bit line sense amplifier 140. Therefore, the upper bit line separator 120A separates/connects the upper memory cell 110 from/to the bit line sense amplifier 140 in response to an upper separation signal BISH, and the lower bit line separator 120B separates/connects the lower memory cell from/to the bit line sense amplifier 140 in response to a lower separation signal BISL.
The bit line equalizer 130 is used to equalize or precharge a bit line BL and a bit line bar /BL to a precharge voltage VBLP in response to an equalization signal BLEQ. Here, a level of the precharge voltage VBLP is half the level of a core voltage (VCORE).
The bit line sense amplifier 140 senses a slight voltage difference between the bit line BL and the bit line bar /BL to amplify one of the bit lines BL and /BL to a voltage level of a pull-up power line RTO and amplify the other one of the bit lines BL and /BL to a voltage level of a pull-down power line SB.
The column selector 160 transfers data amplified by the bit line sense amplifier 140 to a segment line pair SIO and /SIO in response to a column select signal YI that is activated in a read operation. For reference, the data transferred to the segment line pair SIO and /SIO are inputted to an input/output (I/O) sense amplifier (not shown) through a local I/O line pair (not shown) and then re-amplified. The re-amplified data are transferred to a data I/O pad (not shown) through a global I/O line pair (not shown) and then outputted to the outside.
The power supply 150 supplies a power to the bit line sense amplifier 140 through the pull-up power line RTO and the power-down power line SB. The power supply 150 includes a power line equalization unit 152, a pull-up power supply unit 154A, a pull-down power supply unit 154B and an overdriving power supply unit 156.
The power line equalization unit 152 equalizes or precharges the pull-up and pull-down power lines RTO and SB to the precharge voltage VBLP in response to the equalization signal BLEQ. The pull-up power supply unit 154A supplies a core voltage VCORE to the pull-up power line RTO in response to a pull-up driving control signal SAP. The pull-down power supply unit 154B supplies a ground voltage VSS to the pull-down power line SB in response to a pull-down driving control signal SAN. The overdriving voltage supply unit 156 is used to short a VCORE terminal and an external voltage (VDD) terminal in response to an overdriving control signal OVDP.
FIG. 2 is a simulation graph illustrating an active operation and a precharge operation of the upper memory cell 110 in FIG. 1.
Referring to FIGS. 1 and 2, before a word line WL is enabled, the bit line pair BL and /BL is equalized or precharged to the precharge voltage VBLP due to the equalization signal BLEQ of logic high level, and the pull-up and pull-down power lines RTO and SB are also equalized or precharged to the precharge voltage VBLP.
After such a precharge operation, when the word line WL is enabled to trigger charge sharing between the upper memory cell 110 and the bit line BL, a slight voltage difference begins to occur between the bit line BL and the bit line bar /BL. Here, it is assumed that data of logic low level is stored in the upper memory cell 110 for convenience in description. From the assumption, a voltage level of the bit line BL is slightly lowered due to the data of logic low level stored in the upper memory cell 110.
Subsequently, the pull-up driving control signal SAP, the pull-down driving control signal SAN and the overdriving control signal OVDP are activated after a predetermined time (hereinafter, referred to as ‘sensing margin time’) that is sufficient for allowing the bit line sense amplifier 140 to sense the slight voltage difference between the bit line BL and the bit line bar /BL. The pull-up power line RTO is driven to the core voltage VCORE and the pull-down power line SB is driven to the ground voltage VSS. Accordingly, the bit line sense amplifier 140 performs an amplification operation such that a voltage level of the bit line bar /BL is rapidly increased and a voltage level of the bit line BL is rapidly decreased.
To rapidly amplify the bit line pair BL and /BL, an overdriving scheme has been recently adopted in the semiconductor memory device. In the overdriving scheme, the VCORE terminal and the VDD terminal are shorted during an initial period of amplifying the bit line pair BL and /BL, thus allowing the voltage level of the corresponding bit line to be rapidly increased.
FIG. 3 is a block diagram illustrating a circuit block configured to generate the pull-up driving control signal SAP and the pull-down driving control signal SAN.
Referring to FIG. 3, the circuit block includes a bit line sense amplifier (BLSA) enable signal generator 310 and a driving control signal generator 330. The BLSA enable signal generator 310 generates an enable signal SA_EN for operating the bit line sense amplifier 140 in response to an active pulse signal ACT_PUL and a precharge pulse signal PCG_PUL. The driving control signal generator 330 generates the pull-up driving control signal SAP and the pull-down driving control signal SAN in response to the enable signal SA_EN.
Here, when the active pulse signal ACT_PUL relative to an active operation is activated, the enable signal SA_EN is activated after the sensing margin time. The driving control signal generator 330 generates the activated pull-up and pull-down driving control signals SAP and SAN in response to the activated enable signal SA_EN.
Thereafter, when the precharge pulse signal PCG_PUL relative to the precharge operation is activated, the enable signal SA_EN is deactivated. The driving control signal generator 330 generates the deactivated pull-up and pull-down driving control signals SAP and SAN in response to the deactivated enable signal SA_EN.
FIG. 4 is a circuit diagram of the BLSA enable signal generator 310 in FIG. 3.
Referring to FIG. 4, the BLSA enable signal generator 310 includes a period signal generating unit 312, a delay unit 314 and an output unit 316.
The period signal generating unit 312 generates a period signal AP in response to the active pulse signal ACT_PUL and the precharge pulse signal PCG_PUL. Here, the active pulse signal ACT_PUL is a pulse signal that is activated to a logic low level for a predetermined time during the active operation, and the precharge pulse signal PCG_PUL is a pulse signal that is activated to a logic low level for a predetermined time during the precharge operation. Therefore, the period signal AP has a logic high level in response to the active pulse signal ACT_PUL and has a logic low level in response to the precharge pulse signal PCG_PUL.
The delay unit 314 delays the period signal AP by a predetermined delay time, and particularly, it delays a rising edge of the period signal AP from a logic low level to a logic high level. This will be more fully described below.
The output unit 316 generates the enable signal SA_EN according to the period signal AP and an output signal of the delay unit 314. The enable signal SA_EN is activated after the delay time, i.e., the sensing margin time, of the delay unit 314 from the activation timing of the active pulse signal ACT_PUL. The enable signal SA_EN is deactivated at the activation timing of the precharge pulse signal PCG_PUL.
An overall operation will be described briefly below.
First, when the precharge pulse signal PCG_PUL is activated to a logic low level, the period signal AP goes to a logic low level and the enable signal SA_EN goes to a logic low level.
When the active pulse signal ACT_PUL is activated to a logic low level, the output unit 316 outputs the enable signal SA_EN of logic low level continuously although the period signal AP is at a logic high level. Thereafter, the delay unit 314 delays the rising edge of the period signal AP by a predetermined delay time and outputs the delayed period signal, and thus the output unit 316 outputs the enable signal SA_EN of logic high level. Herein, the predetermined delay time of the delay unit 314 corresponds to the sensing margin time.
The enable signal SA_EN, which is activated after the sensing margin time in response to the active pulse signal ACT_PUL, is inputted to the driving control signal generator (330 of FIG. 3), and the driving control signal generator (330) activates the pull-up and pull-down driving control signals SAP and SAN. Afterwards, when the precharge pulse signal PCG_PUL is activated to a logic low level again, the enable signal SA_EN is deactivated to a logic low level, and the pull-up and pull-down driving control signals SAP and SAN are also deactivated.
Referring back to FIGS. 1 and 2, the sensing margin time, which is a time taken from the timing when the word line WL is enabled until the bit line sense amplifier 140 is driven, is one of very critical factors in designing a semiconductor memory device. If the sensing margin time is too short, a voltage difference between the bit line BL and the bit line bar /BL is not sufficient so that unwanted data may be amplified although the bit line sense amplifier 140 is operated. By contrast, if the sensing margin time is too long, the amplification timing of the data is delayed, leading to a decrease in an operating speed. That is, characteristics of a RAS to CAS delay (tRCD) set by specification become poor.
Referring to FIG. 4 again, the delay unit 314 includes first to fourth inverters 314A, 314B, 314C and 314D. Since the first to fourth inverters 314A, 314B, 314C and 314D have the same configuration, following description will be focused on only the first inverter 314A.
The first inverter 314A includes a PMOS transistor PM configured to be pull-up driven in response to the period signal AP of logic low level, an NMOS transistor configured to be pull-down driven in response to the period signal AP of logic high level, and a resistor R for an RC delay.
The resistor R is used to delay the rising edge of the period signal AP because the rising edge of the period signal AP is delayed by the sensing margin time and thus the enable signal SA_EN should be transited to a logic high level in response to the delayed period signal. As described above, when the period signal AP goes to a logic low level, the enable signal SA_EN goes to a logic low level regardless of the output signal of the delay unit 314.
Each resistor in the second to fourth inverters 314B, 314C and 314D as well as the resistor R of the first inverter 314A employs an N+ active resistor doped with N+ dopant in consideration of its area, voltage and temperature variations. However, the resistance of the N+ active resistor may be considerably changed depending on a process variation. This means that the sensing margin time ensured by the delay unit 314 may be changed.
In other words, the resistance of the N+ active resistor may be changed depending on the process variation, thereby changing the sensing margin time. Accordingly, the sensing margin time may be longer or shorter than a target sensing margin time. Consequently, if the sensing margin time becomes too short, unwanted data are amplified. On the contrary, if the sensing margin time becomes too long, characteristics of tRCD become poor.